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108
XMEGA A [MANUAL]
8077I–AVR–11/2012
Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for
ClkSYS.
9.3.2
Oscillator Startup
After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values are automatically loaded from
the production signature row to the calibration registers.
9.4
Reset Sources
9.4.1
Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCCthan for rising VCC. Consult the datasheet for POR characteristics data.
Figure 9-2.
MCU startup, RESET tied to V
CC.
Figure 9-3.
MCU startup, RESET extended externally,
9.4.2
Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
When the BOD is enabled and VCC decreases to a value below the trigger level (VBOT- in Figure 9-4), the brownout reset
is immediately activated.
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
VCC
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